This invention relates to wideband code division multiple access (WCDMA) for a communication system and more particularly to a high-speed generator circuit for generating a Long Code an arbitrary delay.
Present wideband code division multiple access (WCDMA) systems are characterized by simultaneous transmission of different data signals over a common channel by assigning each signal a unique code. This unique code is matched with a code of a selected receiver to determine the proper recipient of a data signal. Base stations in adjacent cells or transmit areas also have a unique pseudorandom noise (PN) code associated with transmitted data. This PN code or Long Code is typically generated by a Linear Feedback Shift Register (LFSR), also known as a Linear Sequence Shift Register, and enables mobile stations within the cell to distinguish between intended signals and interference signals from other base stations. Identification of a PN code requires the mobile station to correctly identify an arbitrary part of the received PN sequence. The identification is frequently accomplished by a sliding window comparison of a locally generated PN sequence with the received part of the PN sequence. The sliding window algorithm often requires the mobile station to efficiently calculate multiple offsets from the LFSR to match the received sequence.
In another application of an LFSR, the base station typically generates a PN sequence for the forward link by a combination of one or more LFSRs 100, 120 as in FIG. 1. The mobile unit is also generates a PN sequence for the reverse link with LFSR circuits 200, 220 as in FIG. 2. This PN sequence is used for quadrature phase shift keyed (QPSK) reverse link transmission. This transmission requires that the PN sequence be arbitrarily shifted by the number of chips equivalent to 250 microseconds for transmitting the in-phase component and the quadrature component. This arbitrary shift may vary with data rate.
The LFSR of FIG. 1 includes two 18-bit shift registers 100 and 120 operated by a clock signal (not shown) to continuously shift the register contents from left to right. A logic gate 110 receives signals from bit positions 0 and 7 of register 100 on leads 108 and 107, respectively, and produces an exclusive OR output signal on lead 102. The output signal is shifted into the most significant bit position (MSB) each clock cycle as the least significant bit (LSB) is shifted out on lead 104. Logic gate 130 receives signals from bit positions 0, 5, 7, and 10 of register 120 on leads 128, 122, 123, and 124, respectively, and produces an exclusive OR output signal on lead 126. The output signal is shifted into the MSB position each clock cycle as the LSB is shifted out on lead 116. Exclusive OR gate 112 receives the signals on leads 104 and 116 and produces a PN code on lead 114. The LFSR embodiment of FIG. 2 includes two 41-bit shift registers 200 and 220 operated in the same manner as the LFSR of FIG. 1. A logic gate 210 receives signals from bit positions 0 and 3 of register 200 on leads 208 and 207, respectively, and produces an exclusive OR output signal on lead 202. The output signal is shifted into the MSB position as the LSB is shifted out on lead 204. Logic gate 230 receives signals from bit positions 0 and 20 of register 220 on leads 228 and 222, respectively, and produces an exclusive OR output signal on lead 226. The output signal is shifted into the MSB position each clock cycle as the LSB is shifted out on lead 216. Exclusive OR gate 212 receives the signals on leads 204 and 216 and produces a PN code on lead 214. Although LFSRs of FIG. 1 and FIG. 2 efficiently generate long PN sequences, neither is readily adaptable to produce arbitrary offsets within their respective PN sequences.
Another application of an arbitrary offset LFSR arises for spreading and despreading transmitted signals as disclosed in U.S. Pat. No. 5,228,054 by Timothy I. Rueth and incorporated herein by reference. Rueth discloses an advantage of modulating each data bit at a constant chip rate for various transmit data rates. For example, a constant chip rate produces 128 chips for each bit at 9600 bits per second and 256 chips for each bit at 4800 bits per second. Thus, the chip rate may remain constant while the transmitted data rate may vary in response to rate information from a base station. Rueth further teaches that synchronization of base and mobile stations is simplified by inserting a zero in the PN sequence, thereby increasing the number of states from 2Nxe2x88x921 to 2N. Synchronization is further simplified by including an arbitrary offset circuit for the LFSR. Rueth teaches a mask circuit 30 in combination with an N-bit LFSR 10 (FIG. 2) for producing a PN offset with respect to the LFSR state. The mask circuit 30 produces the desired offset in response to a mask signal MASK on bus 32. Rueth gives a specific example of a particular mask signal for a 10-chip offset for an exemplary 4-bit LFSR (col. 7, lines 37-40). Rueth, however, fails to teach or suggest how the mask signal is generated for this specific case or how the mask signal might be generated for an LFSR of arbitrary length. Rueth states that xe2x80x9cit would be simplest to implement if the paired values of OFFSET and MASK were pre-computed and stored in a Read Only memory (ROM) not shown.xe2x80x9d (col. 8, lines 63-66). For a 15-bit LFSR, however, this would require 2Nxe2x88x922 (32,722) 15-bit masks. A particular problem with generation of this mask signal, therefore, is the need for a simple circuit to generate states with an arbitrary offset from an LFSR state. Other problems include the practical memory limitation of mobile handsets, calculation complexity of offset determination and speed and power requirements to generate the offset.
These problems are resolved by a circuit designed with a first register circuit arranged to store a state matrix. A memory circuit is arranged to store a plurality of addressable matrices. A control circuit is coupled to receive a delay value and a clock signal. The control circuit is arranged to address a selected matrix from the plurality of addressable matrices in response to the delay value and the clock signal. A backward register circuit is coupled to receive the selected matrix. The backward register circuit is arranged to produce a plurality of shifted matrices from the selected matrix in response to the clock signal. A logic circuit is coupled to receive the state matrix, the selected matrix and the plurality of shifted matrices. The logic circuit produces a logical combination of the state matrix and each of the selected matrix and the plurality of shifted matrices.
The present invention produces a state vector with an arbitrary offset from an initial state vector with minimal power and gate delay. Memory storage requirements for companion matrices are minimized.